Memory integrated circuits commonly use a differential amplifier between the bit cell array and the data output signals which are provided external to the memory. The differential amplifier detects a small voltage difference and amplifies that small voltage difference into a larger voltage difference, e.g. CMOS (complementary metal oxide semiconductor) levels. It is also common for memories to latch the data output signals between the differential amplifier and the data I/O pad in order to provide a consistent logic level one or logic level zero at the data I/O pad while the differential amplifier is detecting the next data value. Prior art circuits exist which use two clock signals: one clock signal to clock the differential amplifier portion, and one clock signal to clock the latch portion of the memory output stage. A problem arises, however, when the timing relationship between the two clocks cannot be consistently controlled due to manufacturing process variations, temperature variations, power supply voltage variations, etc. It is thus advantageous to develop a memory output stage circuit that does not require two or more clocks, and thus does not require that a precise timing relationship between two or more clocks be maintained. In addition, it is advantageous for the memory output stage to be as fast as possible.